1. Field of the Invention
The present invention relates generally to the design of analog to digital converters (ADC) and more specifically to method and apparatus providing efficient amplifier sharing in a multi_stage ADC.
2. Related Art
An analog to digital converter (ADC) is generally used to sample an analog signal at various time instances, and generate digital codes representing the strength of the sampled analog signal at the corresponding time instances. Typically, high resolution (representing each digital code in a large number of digital bits) ADCs are implemented using multiple stages. A pipelined ADC is a type of ADC which contains multiple stages, with each stage resolving a number of bits forming a sub-code. The sub-codes generated by various stages are used to generate a digital code corresponding to the sampled analog signal.
Each stage of an ADC generally needs an amplifier to amplify a residue signal representing a difference of the voltage level of the input signal and the voltage equivalent of the generated sub-code. For example assuming a stage generates a sub-code equaling S, the residue signal equals (Vin−(S*Vref/2p)), wherein p represents the number of bits in the sub-code S, Vref represents a reference voltage and Vin represents sampled input signal.
The amplifier amplifies the residue signal generally with a gain of 2p and provides the amplified residue signal as an input signal to the next stage. According to one prior approach, each stage is provided with a separate amplifier to provide the desired amplification for the stage. In the corresponding embodiments, the amplifier may not be utilized in some time durations (e.g., in sampling phase of the stage, as described with examples below), and the amplifier may continue to consume power in such un-utilized durations, as well. As a result, unacceptably large amount of power may be consumed by each of such stages.
In order to reduce the overall power consumption of the ADC, an amplifier is shared between two stages in a time multiplexed manner. For example, in one prior embodiment, an amplifier is used to amplify the residue signal of one stage in a first time duration and the same amplifier is used to amplify the residue signal of the other stage in a second time duration. Due to the reduction of the un-utilized time duration compared to the prior embodiment described in the above paragraph(s), the aggregate power consumption due to the two stages is reduced.
Even while using such techniques, there is a general need to minimize non-linearity and power consumption in analog to digital converters.
In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit (s) in the corresponding reference number.